In a flat display panel, a gate turn-on signal is typically provided to a gate of a respective Thin Film Transistor (TFT) of a pixel region by a gate driving circuit. The gate driving circuit may be formed on an array substrate of the flat display panel through an array process, i.e., a Gate Driver on Array (GOA) process. This integration process not only saves cost, but also achieves an aesthetic design in which the flat display panel is bilaterally symmetrical. Meanwhile, a bonding area of a gate Integrated Circuit (IC) and a wiring space of Fan-out are omitted, therefore achieving a design with a narrow border.
As illustrated in FIG. 1, the existing gate driving circuit consists of multiple cascaded shift register units, SR(1), SR(2) . . . SR(n), SR(n+1) . . . SR(N−1), SR(N) (N shift register units in total, with 1≤n≤N), and each stage of the shift register unit SR(n) is used for providing a gate turn-on signal to a gate line connected with a signal output terminal Output_n of the stage of the shift register unit SR(n), so as to turn on a TFT of a pixel region of a corresponding line. Wherein, each of the signal input terminals Input_n of the remaining stages of the shift register units SR(n) except for a first stage of shift register unit SR(1) is connected to a signal output terminal Output_n−1 of a previous stage of shift register units SR(n−1). Each stage of shift register units SR(n) includes a pull-up node for controlling the signal output terminal to output the gate turn-on signal, and when the potential of the pull-up node is further pulled up, the signal output terminal outputs the gate turn-on signal.
Presently, in a touch display panel in which touch and display are driven at different times (i.e., multiple touch periods are inserted in the time of displaying one frame of picture, and in general each touch period needs a time interval with a certain duration), assuming that a touch period is entered after the outputting of the gate turn-on signal by the signal output terminal of the nth stage of the shift register unit is completed, at this time, the potential of the pull-up node in a(n+1)th stage of shift register unit has already become a high potential, the interval of the touch period is relatively long, during which a leakage will occur through a TFT to which the pull-up node in the (n+1)th stage of shift register unit is connected, which will lead to a potential reduction in the pull-up node. When the touch period ends, the (n+1)th stage of shift register unit starts to operate. Since the potential of its pull-up node is reduced, the gate turn-on signal output by the signal output terminal of the shift register unit will also be reduced, which may even lead to a situation in which the TFT in the pixel region cannot be turned on, and eventually cause an abnormal operation of the touch display panel.